`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   01:29:13 05/05/2013
// Design Name:   fpga_top
// Module Name:   C:/Users/jboedin/Desktop/LAB2/fpga_top_tb.v
// Project Name:  LAB2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: fpga_top
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_fpga_top;

	// Inputs
	reg [7:0] sw;
	reg btnLOAD;
	reg btnRST;
	reg btnGO;
	reg clk;

	// Outputs
	wire [6:0] seg;
	wire [3:0] an;
	wire [1:0] led;

	// Instantiate the Unit Under Test (UUT)
	fpga_top # (
		.BUTTONHYS_ON(6), 
		.BUTTONHYS_OFF(3),
		.SWITCHHYS_ON(6),
		.SWITCHHYS_OFF(3),
		.ECDURATION(1000)
		) uut (
		.sw(sw), 
		.btnLOAD(btnLOAD), 
		.btnRST(btnRST), 
		.btnGO(btnGO), 
		.clk(clk), 
		.seg(seg), 
		.an(an), 
		.led(led)
	);

	initial begin
		clk = 1'b0;
		forever #5 clk = !clk;
	end

	initial begin
		// Initialize Inputs
		sw = 0;
		btnLOAD = 0;
		btnRST = 1;
		btnGO = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
 		btnRST = 0;
       
		// Load RegA
		sw = 8'b01010000;
		#100;
		btnLOAD = 1'b1;
		#100;
		btnLOAD = 1'b0;

		// Load RegB
		sw = 8'b11110100;
		#100;
		btnLOAD = 1'b1;
		#100;
		btnLOAD = 1'b0;
		
		// ADD AB
		sw = 8'b01001001;
		#100;
		btnLOAD = 1'b1;
		#100;
		btnLOAD = 1'b0;
		
		#1000;
		btnGO = 1'b1;
		
		#1000000;
		btnRST = 1;

	end
      
endmodule

